Some storage devices are provided with a function called memory interleave, which is configured to bring the speed of a memory access operation closer to the speed of a high-speed processor. The memory interleave function is configured to divide a memory into a plurality of (for example, two) areas called banks, enable each of the divided banks to independently operate, and carry out read/write simultaneously or alternately.
In a storage device described in Japanese Patent No. 2689452, starting circuits 1-0 and 1-1 provided in a bank 0 and bank 1, and capable of operating parallel to each other receive a command to carry out read or write, and an access request signal R1 configured to designate a bank, address, and data length for the command, and output a start request signal S0 or S1 configured to start an access operation of the designated bank 0 or bank 1. When the designated address and data length extend to the next bank 1 or bank 0, the starting circuits 1-0 and 1-1 issue a command to carry out read or write for the next bank 1 or bank 0, and an access request signal R2 or R3 designating a next bank for the command, subsequent address, and remaining data length.
Further, address generating circuits 2-0 and 2-1 respectively provided in the bank 0 and bank 1 receive a start request signal S0 or S1 from the starting circuit 1-0 or 1-1, generate a signal configured to select an address for each word which is a data address unit, in sequence from the designated address in a designated bank up to an address of a boundary of the bank or the last address of the designated data length, and output the generated signals collectively as four address selection signals A0, A1, A2, and A3 in data access units.
According to the storage device described in the patent document, it is possible to carry out block transfer at high speed or carry out interleave transfer at high speed according to the contents of the access request signal. This makes it possible to operate both data having consecutive addresses and data having nonconsecutive addresses at a high processing speed.
In the device described in the patent document, a memory address configured to access the memory interleave is generated from an immediately preceding request address. As a result of this, it is necessary for interleave-controlled addresses to be related to each other by way of an address generation circuit, and hence it is not possible to carry out arbitrary addressing.
Further, interleave control data is sent after completion of transfer of one transfer unit (for example, 512 bytes) of write data or read data. As a result of this, the transfer time of the whole data is prolonged by the transfer time of the interleave control data.